This invention relates to a communication apparatus having an outer-loop power control function and to an outer-loop power control method. More particularly, the invention relates to a communication apparatus having an outer-loop power control function and to an outer-loop power control method for increasing target SIR if an error is detected in a block-error observation interval and decreasing target SIR if not a single error is detected in the block-error observation interval.
In CDMA mobile communications, multiple channels are distinguished from one another by spreading codes that are assigned to the channels, whereby a plurality of channels perform communication sharing a single frequency band. In an actual mobile communications environment, however, a received signal is susceptible to interference from its own channel and from other channels owing to delayed waves ascribable to multipath fading and radio waves from other cells, and this interference has an adverse influence upon channel separation. Further, the amount of interference sustained by a received signal varies with time owing to momentary fluctuations in reception power ascribable to multipath fading and changes in the number of users communicating simultaneously. In an environment in which a received signal is susceptible to noise that varies with time in this fashion, it is difficult for the quality of a received signal in a mobile station linked to a base station to be maintained at a desired quality in a stable manner.
In order to follow up such a change in number of interfering users and a momentary fluctuation caused by multipath fading, inner-loop transmission power control is carried out for exercising control in such a manner that signal-to-interference ratio (SIR) is measured on the receiving side and the measured value is compared with a target SIR, whereby SIR on the receiving side will approach the target SIR.
FIG. 37 is a diagram for describing inner-loop transmission power control. Here only one channel is illustrated. A spread-spectrum modulator 1a of a base station 1 spread-spectrum modulates transmit data using a spreading code conforming to a specified channel. The spread-spectrum modulated signal is subjected to processing such as orthogonal modulation and frequency conversion and the resultant signal is input to a power amplifier 1b, which amplifies this signal and transmits the amplified signal toward a mobile station 2 from an antenna. A despreading unit 2a in the receiver of the mobile station applies despread processing to the received signal and a demodulator 2b demodulates the received data. A SIR measurement unit 2c measures the power ratio between the received signal and an interference signal and a comparator 2d compares target SIR and measured SIR. If the measured SIR is greater than the target SIR, the comparator 2d creates a command that lowers the transmission power by TPC (Transmission Power Control) bits. If the measured SIR is less than the target SIR, the comparator 2d creates a command that raises the transmission power by the TPC bits. The target SIR is a SIR value necessary to obtain, e.g., 10−3 (error occurrence at a rate of once every 1000 times). This value is input to the comparator 2d from a target-SIR setting unit 2e. A spread-spectrum modulator 2f spread-spectrum modulates the transmit data and TPC bits. After spread-spectrum modulation, the mobile station 2 subjects the signal to processing such as a DA conversion, orthogonal modulation, frequency conversion and power amplification and transmits the resultant signal toward the base station 1 from an antenna. A despreading unit 1c on the side of the base station applies despread processing to the signal received from the mobile station 2, and a demodulator 1d demodulates the received data and TPC bits and controls the transmission power of the power amplifier 1 in accordance with a command specified by the TPC bits.
FIG. 38 is a diagram showing an uplink frame structure standardized by the 3rd Generation Partnership Project (referred to as “3GPP” below). There is a DPDCH data channel (Dedicated Physical Data Channel) on which only transmit data is transmitted, and a DPCCH control channel (Dedicated Physical Control Channel) on which a pilot and control data such as TPC bit information, described above with reference to FIG. 37, are multiplexed. After each of these is spread by an orthogonal code, they are mapped onto real and imaginary axes and multiplexed. One frame of the uplink has a duration of 10 ms and is composed of 15 slots (slot #0 to slot #14). The DPDCH data channel is mapped to an orthogonal I channel of QPSK modulation and the DPCCH control channel is mapped to an orthogonal Q channel of QPSK modulation. Each slot of the DPDCH data channel (I channel) consists of n bits, and n varies in accordance with the symbol rate. Each slot of the DPCCH control channel (Q channel) that transmits the control data consists of ten bits, has a symbol rate of 15 ksps and transmits a pilot PILOT, transmission power control data TPC, a transport format combination indicator TFCI and feedback information FBI.
Owing to changes in traveling velocity during communication and changes in the propagation environment ascribable to travel, the SIR that is necessary to obtain a desired quality (the block error rate, or BLER) is not constant. In order to deal with these changes, block error is observed and control is exercised to increase the target SIR if the observed value is inferior to the target BLER and decrease the target SIR if the observed value is superior to the target BLER. Control that thus changes the target SIR adaptively in order to achieve the desired quality is well known as outer-loop transmission power control (outer-loop TPC). Schemes indicated in [1] 2001 Electronic Information Communications Society Convention, B-5-56, [2] Shingaku Giho RCS 98-18 pp. 51–57, [3] 1999 Electronic Information Communications Society Convention, B-5-145, and [4] 2000 Electronic Information Communications Society Convention, B-5-72, are available as outer-loop control schemes.
FIG. 39 is a block diagram of outer-loop control proposed in Reference [1]. According to this scheme, a signal that has been transmitted from the base station 3 is decoded by an error correcting decoder 4b after it is demodulated by a demodulator 4a. The decoded signal is then divided into transport blocks TrBk by a CRC detector 4c and subsequently subjected to CRC error detection on a per-TrBk basis. The result of error detection applied to each transport block TrBk is sent to target-SIR controller 4d. 
In W-CDMA as currently standardized, encoding is performed on the transmitting side in the manner shown in FIG. 40. Specifically, if a plurality (N) of transport blocks TrBk exist in a unit transmission time (Transmission Time Interval: TTI), a CRC add-on circuit generates a CRC (Cyclic Redundancy Code) error-detecting code for every transport block TrBk and adds this onto the transmit data. An encoder joins the N-number of transport blocks TrBk having the attached CRCs and encodes the blocks by error-correcting encoding such as convolutional coding or turbo coding. On the receiving side the error correcting decoder 4b subjects the received data to error-correction decoding processing and inputs the result of decoding to the CRC detector 4c. The CRC detector 4c performs CRC error detection for every transport block TrBk constituting the result of decoding and inputs the results of error detection to the target-SIR controller 4d. 
As shown in FIG. 41, the target-SIR controller 4d controls the target SIR through a procedure of the kind shown in FIG. 41. Specifically, at the start of control of the target SIR, the target-SIR controller 4d reads in parameters (observation interval T, incrementing step Sin c and decrementing step Sdec), which conform to the target BLER, from a parameter conversion table 4e, stores the parameters in an internal storage register 5a and resets the content (received-block count N) of a received-block counter 5b (steps S01, S02). It should be noted that a number of the observation intervals T, incrementing steps Sin c and decrementing steps Sdec have been stored in the parameter conversion table 4e beforehand in accordance with various target BLERs and therefore the parameters conforming to the currently set target BLER are read out and stored in the storage register 5a. 
If the CRC detector 4c receives a decoded result (consisting of one or more transport blocks TrBk) from the error correcting decoder 4b under these conditions (step S03), it subjects the decoded result to CRC error detection every transport block TrBk and inputs the result of error detection to the target-SIR controller 4d (step S04). Upon receiving the result of CRC error detection, the target-SIR controller 4d determines whether an error has been detected (step S05).
If the number or erroneous blocks in CRC detection is one or more, then the target-SIR controller 4d uses a target-SIR increase/decrease controller 5c to increase the target SIR by Sin c (step S06). The target-SIR controller 4d subsequently returns control to step S02, resets the number of received blocks and repeats processing from step S03 onward.
If the number or erroneous blocks in CRC detection is zero, then the target-SIR controller 4d adds a TrBk count NBLK in the current transmission time interval TTI to the received-block count N (the initial value of which is zero) (step S07). Next, the target-SIR controller 4d determines whether the received-block count is equal to or greater than the block count that corresponds to the observation interval T (step S08).
If the received-block count N is equal to or greater than the block count corresponding to the observation interval T, then this means that not a single error was detected in the observation interval. Accordingly, the target-SIR controller 4d uses the target-SIR increase/decrease controller 5c to decrease the target SIR by Sdec (step S09), returns control to step S02, resets the count of received blocks and repeats processing from step S03 onward.
The target-SIR controller 4d outputs the target SIR, which has been updated at steps S06, S09, to a comparator 4f. The latter compares the measured SIR obtained by a SIR measurement unit 4g with the target SIR and, on the basis of the result of the comparison, creates a TPC command that is transmitted to the base station 3.
In this conventional outer-loop power control method, the target SIR is increased or decreased as indicated in FIG. 42(A) if the number of TrBks in the TTI is one, and the target BLER can be attained. However, if the number of TrBks in the TTI is two or more and an error occurs is a plurality of TrBks, the target BLER can no longer be attained. The reason for this will be described. If the number of TrBks in the TTI is plural (N in number), then the CRC detector 4c separates the results of decoding on a per-TrBk basis and subjects each TrBk to CRC error detection, as described in accordance with FIG. 40. From the viewpoint of the nature of the error-correcting code, there are many cases where all N-number of transport blocks TrBk contain an error if an error exists in decoded data. The reasons for this are as follows:
{circumflex over (1)} error in the transmission path is dispersed over all of the code blocks because interleaving is applied to the data after encoding is performed; and
{circumflex over (2)} interleaving is also applied internally of a turbo decoder in a case where turbo encoding is employed.
In a case where error occurs in the manner described above, error is detected in almost all of the transport blocks TrBk within the TTI. Therefore, in an arrangement in which the conventional outer-loop power control method is applied as is, control for updating the target SIR is performed in exactly the same manner as in the case where an error occurs in one TrBk [see FIG. 42(A)] even in a situation where error occurs in N (=4) TrBks within the TTI, as shown in FIG. 42B. Consequently, the BLER obtained as a result deteriorates in comparison with the target BLER and becomes approximately N times the target BLER.
Thus, with the conventional schemes, a problem which arises is that the target BLER cannot be attained in a case where a plurality of error-detecting blocks (transport blocks: TrBk) are contained the transmission time interval (TTI).